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VS6525
VGA single-chip camera module
Data Brief
Features

640H x 480V active pixels 2.2 m pixel size, 1/10 inch optical format RGB Bayer color filter array Integrated 10-bit ADC Integrated digital image processing functions, including defect correction, lens shading correction, demosaicing, sharpening, gamma correction and color space conversion Embedded camera controller for automatic exposure control, automatic white balance control, black level compensation Up to 30 fps progressive scan, integer subsampling and cropping modes ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, RGB 565 output formats Viewlive feature allows different sizes, formats and reconstruction settings to be applied to alternate frames 8-bit parallel video interface, horizontal and vertical syncs, 24 MHz clock Two-wire serial control interface (I2C) On-chip PLL, 6.5 to 26 MHz clock input Analog power supply, from 2.4V to 3.0V Separate I/O power supply, 1.8V or 2.8V levels Integrated power management with power switch, automatic power-on reset and powersafe pins Low power consumption, ultra low standby current Aspheric lens, F# 3.2 ~56 HFOV
Description
The VS6525 is a general purpose VGA resolution CMOS color digital camera featuring low size and low power consumption. This complete camera module is ready to connect to camera enabled baseband processors, back-end IC devices or PDA engines.

Applications

Mobile phone Videophone Video surveillance Medical Machine Vision Toys PDA Biometry Bar code reader Lighting control

January 2007
Rev 1
1/6
www.st.com
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For further information contact your local STMicroelectronics sales office.
Technical specifications
VS6525
1
Technical specifications
Table 1.
Active pixels Pixel size Array size Color filter array Exposure control Analog gain Dynamic range Signal-to-noise Ratio Frame rate Image format
Technical specifications
640H x 480V 2.2 m x 2.2 m 1.408 mm x 1.056 mm RGB Bayer +120 dB +24 dB (max) 61 dB (typical) 35 dB at 100 lux (typical) 1 to 30 Hz VGA, QVGA, QQVGA, subQCIF Arbitrary cropping Horizontal/vertical flipping YUV 4:2:2 RGB 565, RGB 444 Raw Bayer 10-bit 8-bit parallel video, hsync, vsync ITU-R BT.656-4 compliant, 24 MHz max 6.5 to 26 MHz square 13 MHz typ. (on-chip PLL) 2.4 to 3.0 V analog 1.8 V or 2.8 V Streaming 30 fps: TBD Power down: TDB 1-element, ~56 HFOV, F#3.2 20 cm to infinity < 5% 60% typ. Reflowable 4.9 mm x 4.9 mm x 2.8 mm (wlh)
Pixel format
Video Interface
Clock input Supply voltage Separate I/O power supply Current consumption (max) Lens Depth of field TV distortion Relative illumination Package type Package size
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VS6525
Application and block diagrams
2
Figure 1.
Application and block diagrams
Application diagram Figure 2. Block diagram
VS6525 VS6525
VGA camera module SCL, SDA D[7:0] HSYNC VSYNC PCLK FSO CLK CE
CLK PLL and Clock Management Power Mgmt IC Receiver Camera Controller Power-On Reset 640 x 480 Pixel array 1152 x 864
SCL SDA D[7:0] HSYNC, VSYNC PCLK FSO
Parallel Video i/f
Readout
Video Processor
Y Decoder
Baseband or Application Processor
CE
VDD DGND
AVDD AGND
Column ADC X Decoder Line SRAM
3
Ordering information
Table 2. Order codes
Package Reflowable YUV-VGA (4.9mm x 4.9mm x 2.8mm)
Part number VS6525R0EI/T2
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Mechanical drawings
VS6525
4
Mechanical drawings
The following figures present different views of the module with dimensions and pin assignment. Figure 3. Module rear view and connection table
Connection table
Nominal
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13
Function VHIGH AGND D101 D100 AVDD HV GPIO D104 D103 D102 SDA SCL D107
Pad # 14 15 16 17 18 19 20 21 22 23 24 25
Function D105 D106 PORTEST XSHUTDOWN PCLK HSYNC VSYNC VDD PORSGN DGND CAP1V2 EXTCLK
Nominal
Nominal Nominal
Nominal
Nominal
Figure 4.
A
PIN 1 IDENTIFICATION
Module size
REV.
Nominal 4.90 0.10 MOUNT AND SUBSTRATE
1.96 SEE NOTE 2 2.80 Nominal 0.10
A
Z height
N 1 2 B
C
D
ON
D FI
E
I NT
A
O LC
M
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VS6525
Revision history
5
Revision history
Table 3.
Date 12-Jan-2007
Document revision history
Revision 1 Initial release. Changes
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VS6525
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